The present invention generally relates to superconductor circuits and, in particular, to low-inductance resistors for superconductor circuits.
With increasing demand for speed and efficiency in digital circuits, superconductor circuits have found significant application in defense and commercial systems including high-speed super-computers, digital processors, high-performance network switches, analog to digital converters, rf filters, resonators, low-loss transmission lines, mine-detectors and bio-magnetic imagers. The resistor is a most essential component of any superconductor integrated circuit.
A vital component of any superconductor circuit is a resistor. Resistors are utilized as terminating resistors for high-speed transmission lines, bias-current resistors, damping/shunt and/or load line resistors for Josephson Junctions and SQUID (Superconductive Quantum Interference Device) circuits. Depending on the application, resistor values can be as low as one milliohm to as high as 10-100 ohms. With such variance in resistor values, it is necessary to fabricate resistors with different sheet resistivities having low and high values where sheet resistivity is determined by Rs=.rho./T where .rho. is resistivity of the film and T is the thickness expressed in ohms/square of the film. It becomes necessary to use different layout geometries to customize a desired sheet resistance value.
Conventional resistor modules are typically fabricated by: depositing a thin film of resistive material on a substrate; patterning the resistive material to define a resistor structure; depositing a dielectric layer on the resistive film; patterning via contacts to the resistor; depositing a superconductive interconnect layer on the dielectric layer; and patterning a superconductive interconnect layer.
A schematic of a resistor structure fabricated using conventional methods is shown in FIG. 1. The first processing step is to deposit a thin film of resistive material R on a substrate U and to pattern R to define the resistor structure. Overlaying R is next applied a dielectric layer DL. Via contacts are patterned to R and a film of HTS interconnect is grown over the DL. The HTS is patterned. This process results in a non-planar topology. Non-planarity, as schematically represented in FIG. 1, creates grain boundary "GB" zones and etching irregularities e.g., over etching, involving the boundary between HTS and R. The GB zones cause electrical discontinuities and the etching irregularities result in high interface resistance or discontinuities.
A disadvantage of the conventional fabrication methods is the process complexity due to the number of steps involved. Another problem is the potentially high interface contact resistance from the superconductive interconnect layer to the resistor layer. Yet, a further problem is that of potential over-etching associated with etching the vias in dielectric layer over the very thin resistor film material.
A disadvantage of fabricating resistors for superconductor circuits using conventional methods is that they involved non-planar topologies for the superconductive interconnect layers. A non-planar topology on which is grown a superconductive film encounters ramp discontinuities which can cause open or high resistance connection of the superconductive interconnect layer. It is the ramp boundaries that reduce the super current it can carry and this results in an electrical discontinuity. This problem is particularly severe for niobium nitride and high-temperature superconductors such as copper oxide superconductors. Another disadvantage of such resistors is high parasitic inductance of the resistor structure because of non-planar and complicated topology.
There is, therefore, a need for a process of fabricating a low-inductance resistor with substantially planar topology. There is also a need for a such a process to have fewer steps which are less complex.